library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;

entity MAR is
    port(Clk,LD_MAR: in  bit;
         Bus_in:    in  unsigned(15 downto 0);
         MAR_out:    out unsigned(15 downto 0));
end entity MAR;

architecture build of MAR is
    begin
        process(Clk,LD_MAR,Bus_in)
            begin
                if Clk = '1' and Clk'event then
                    if LD_MAR = '1' then
                        MAR_out <= Bus_in;
                    end if;
               end if;
            end process;
    end build;

